1. Field of the Invention
The present invention relates generally to chemical mechanical polishing (CMP) technology, and more particularly, to a low-stress polishing device.
2. Description of the Related Art
As the technology of semiconductor manufacturing process advances by leaps and bounds and the electronic element is more and more compact, to enhance the operation speed, the semiconductor industry has entered the field of deep submicron, so that the intensity of the elements within unit area is greatly increased and accordingly the interconnect of the chip microminiaturizes. The microminiaturized interconnect incurs high resistance and the small breadth of the interconnect increases the parasitic capacitance to result in more and more serious resistance-capacitance (RC) time delay, thus affecting the operation speed of the electronic element.
Because the delay of signals of the interconnect is the product that the resistance (R) of the metal wire times the capacitance (C) of the dielectric layer, reduction of the signal delay can be done by the following two approaches. The first approach is to replace the prevalent aluminum wire process by the metallic material having low resistance. Because the copper has very low resistance and excellent electromigration, it is deemed as the material that the metal wire is made for the next generation. The other approach is to apply the material having low dielectric constant to the dielectric layer between the metal wires. So far, the low dielectric material has been developed from the oxide of dielectric constant (4) to the fluoroxide of dielectric constant (3.5) toward the ultra low dielectric material whose dielectric constant is smaller than 2. To enable the integrated circuit (IC) to have high-speed performance, the integration of the copper wire and the dielectric having low dielectric constant is the main trend of development of the semiconductor industry at present.
The conventional CMP is still the primary process for removal and polishing treatment on the copper damascene structure in the relevant field. The majority of dielectric materials having ultra-low dielectric constant are porous and such materials are too insufficiently cohesive and too squashy to stand the stress applied thereto under the CMP. For this reason, low-stress polishing approach is required for treatment of the dielectric materials having ultra-low dielectric constant.
The present low-stress polishing approach is mainly developed based on the conventional electropolishing technique. However, when the conventional electropolishing technique is applied to the metal film of the wafer surface for overall planarization, the technical bottleneck happens. Although such polishing process can be applied to polishing treatment of the metal film, when it is applied to the polishing treatment of other materials, like low-dielectric barrier materials (Tantalum, Tantalum Nitride, Titanium, and Titanium Nitride) having greater passivity, applied in the copper process, the planarization process of the electropolishing technique is ineffective in removal of the barrier materials.